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AMMP-6232-BLKG 参数 Datasheet PDF下载

AMMP-6232-BLKG图片预览
型号: AMMP-6232-BLKG
PDF下载: 下载PDF文件 查看货源
内容描述: 18至32 GHz的砷化镓高线性度LNA采用SMT封装 [18 TO 32 GHZ GAAS HIGH LINEARITY LNA IN SMT PACKAGE]
分类和应用: 射频和微波射频放大器微波放大器
文件页数/大小: 9 页 / 559 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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AMMP-6232 Application and Usage
4V
Vdd
1
2
0.1uF
Biasing and Operation
The AMMP-6232 is normally biased with a positive drain
supply connected to the VDD pin and a negative gate
bias through bypass capacitors as shown in Figure 19. The
recommended drain supply voltage is 4 V and the gate bias
is approximately -0.95V to get the corresponding drain
current of 138mA. It is important to have 0.1uF bypass
capacitors and the capacitor should be placed as close
to the component as possible. Aspects of the amplifier
performance may be improved over a narrower bandwidth
by application of additional conjugate, linearity, or low
noise (Topt) matching.
After adjusting the gate bias to obtain 138mA at Vdd = 4V,
the AMMP-6232 can be safely biased at 3V or 5V (while
fixing the gate bias) as desired. At 4V, the performance
is an optimal compromise between power consumption,
gain and power/linearity. It is both applicable to be used
as a low noise block or driver. At 3V, the amplifier is ideal
as a front end low noise block where linearity is not highly
required. At 5V, the amplifier can provide 1 to 2dBm more
output power for LO or transmitter driver applications
where high output power and linearity are often required.
Refer the Absolute Maximum Ratings table for allowed DC
and thermal conditions.
3
100pF
IN
8
4
OUT
100pF
7
6
5
0.1uF
Vg
Top View
Package base: GND
Figure 19. Usage of the AMMP-6232
~ -0.95V
Figure 20. Evaluation/Test Board (available to qualified customer request)
Vd1
Vd2
In
Matching
Network
Matching
Network
Matching
Network
Out
Vg1
Vg2
Figure 21. Simplified AMMP-6232 Schematic
6