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ATF-521P8-TR2 参数 Datasheet PDF下载

ATF-521P8-TR2图片预览
型号: ATF-521P8-TR2
PDF下载: 下载PDF文件 查看货源
内容描述: 高线性度增强模式[ 1 ]赝2×2 mm2的LPCC [ 3 ]包 [High Linearity Enhancement Mode[1] Pseudomorphic 2x2 mm2 LPCC[3] Package]
分类和应用: 晶体晶体管光电二极管放大器PC
文件页数/大小: 23 页 / 304 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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ATF-521P8
High Linearity Enhancement Mode
[1]
Pseudomorphic HEMT in
2x2 mm
2
LPCC
[3]
Package
Data Sheet
Description
Avago Technologies’ ATF‑521P8 is a single‑voltage high
linearity, low noise E‑pHEMT housed in an 8‑lead JEDEC‑
standard leadless plastic chip carrier (LPCC
[3]
) package.
The device is ideal as a medium‑power, high‑linearity
amplifier. Its operating frequency range is from 50 MHz
to 6 GHz.
The thermally efficient package measures only 2mm x
2mm x 0.75mm. Its backside metalization provides ex‑
cellent thermal dissipation as well as visual evidence of
solder reflow. The device has a Point MTTF of over 300
years at a mounting temperature of +85°C. All devices
are 100% RF & DC tested.
Features
• Single voltage operation
• High linearity and P1dB
• Low noise figure
• Excellent uniformity in product specifications
• Small package size:
2.0 x 2.0 x 0.75 mm
3
• Point MTTF > 300 years
[2]
• MSL‑1 and lead‑free
• Tape‑and‑reel packaging option available
Specifications
• 2 GHz; 4.5V, 200 mA (Typ.)
• 42 dBm output IP3
• 26.5 dBm output power at 1 dB gain compression
• 1.5 dB noise figure
• 17 dB Gain
• 12.5 dB LFOM
[4]
Pin Connections and Package Marking
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
Source
(Thermal/RF Gnd)
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Pin 8
Applications
• Front‑end LNA Q2 and Q3, driver or pre‑driver amplifier
for Cellular/PCS and WCDMA wireless infrastructure
• Driver amplifier for WLAN, WLL/RLL and MMDS applica‑
tions
• General purpose discrete E‑pHEMT for other high linear‑
ity applications
2Px
Top View
Pin 7 (Drain)
Pin 6
Pin 5
Note:
Package marking provides orientation and identification
“2P” = Device Code
“x” = Month code indicates the month of manufacture.
Note:
1. Enhancement mode technology employs a single positive V
gs
,
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed MTTF data
3. Conform to JEDEC reference outline MO229 for DRP‑N
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC
bias power.
Attention:
Observe precautions for handling electrostatic
sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 1C)
Refer to Avago Technologies Application Note A004R: Electrostatic
Discharge Damage and Control.