vary from 0 to 5.5 V without
affecting either the Dot or the
Electrostatic Discharge
Appendix D. Refresh Circuitry
This display driver consists of
20 one-of-eight column decoders
and 20 constant current sources,
1 one-of-eight row decoder and
eight row sinks, a pulse width
modulation control block, a peak
current control block, and the
circuit to refresh the LEDs. The
refresh counters and oscillator
are used to synchronize the
columns and rows.
The inputs to the ICs are pro-
tected against static discharge
and input current latchup. How-
ever, for best results, standard
CMOS handling precautions
should be used. Before use, the
HCMS-29XX should be stored in
antistatic tubes or in conductive
material. During assembly, a
grounded conductive work area
should be used and assembly
personnel should wear conduc-
tive wrist straps. Lab coats made
of synthetic material should be
avoided since they are prone to
static buildup. Input current
latchup is caused when the
Control Registers. V
can be
LED
varied between 4.0 to 5.5 V with-
out any noticeable variation in
light output. However, operating
V
below 4.0 V may cause
LED
objectionable mismatch between
the pixels and is not
recommended. Dimming the
display by pulse width modulat-
ing V
is also not
LED
recommended.
The 160 bits are organized as 20
columns by 8 rows. The IC
illuminates the display by
V
can vary from 3.0 to 5.5 V
LOGIC
without affecting either the
displayed message or the display
intensity. However, operation
below 4.5 V will change the
timing and logic levels and
operation below 3 V may cause
the Dot and Control Registers to
be altered.
sequentially turning ON each of
the 8 row-drivers. To refresh the
display once takes 512 oscillator
cycles. Because there are eight
row drivers, each row driver is
selected for 64 (512/8) oscillator
cycles. Four cycles are used to
briefly blank the display before
the following row is switched on.
Thus, each row is ON for 60
oscillator cycles out of a possible
64. This corresponds to the
CMOS inputs are subjected to
either a voltage below ground
(V < ground) or to a voltage
IN
higher then V
(V
>
LOGIC
IN
V
) and when a high current
LOGIC
is forced into the input. To
The logic ground is internally
connected to the LED ground by
a substrate diode. This diode
becomes forward biased and
conducts when the logic ground
is 0.4 V greater then the LED
ground. The LED ground and the
logic ground should be
connected to a common ground
which can withstand the current
introduced by the switching LED
drivers. When separate ground
connections are used, the LED
ground can vary from -0.3 V to
+0.3 V with respect to the logic
ground. Voltages below -0.3 V
can cause all the dots to be ON.
Voltage above +0.3 V can cause
dimming and dot mismatch. The
LED ground for the LED drivers
can be routed separately from
the logic ground until an
prevent input current latchup
and ESD damage, unused inputs
should be connected to either
ground or V
. Voltages
LOGIC
should not be applied to the
inputs until V has been
maximum LED on time.
LOGIC
applied to the display.
Appendix E. Display Brightness
Two ways have been shown to
control the brightness of this
LED display: setting the peak
current and setting the duty
factor. Both values are set in
Control Word 0. To compute the
resulting display brightness
when both PWM and peak
current control are used, simply
multiply the two relative bright-
ness factors. For example, if
Control Register 0 holds the
word 1001101, the peak current
Appendix C. Oscillator
The oscillator provides the
internal refresh circuitry with a
signal that is used to synchron-
ize the columns and rows. This
ensures that the right data is in
the dot drivers for that row. This
signal can be supplied from
either an external source or the
internal source.
A display refresh rate of 100 Hz
or faster ensures flicker-free
operation. Thus for an external
oscillator the frequency should
be greater than or equal to 512 x
100 Hz = 51.2 kHz. Operation
above 1 MHz without the
prescaler or 8 MHz with the
prescaler may cause noticeable
pixel to pixel mismatch.
is 73% of full scale (BIT D = L,
5
BIT D = L) and the PWM is set
4
appropriate ground plane is
available. On long
interconnections between the
display and the host system,
voltage drops on the analog
ground can be kept from
to 60% duty factor (BIT D = H,
3
BIT D = H, BIT D = L, BIT D =
2
1
0
H). The resulting brightness is
44% (.73 x .60 = .44) of full scale.
affecting the display logic levels
by isolating the two grounds.
15
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
