AC Timing Characteristics Over Temperature Range (-40°C to +85°C)
Timing
Diagram Ref.
Number
Description
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
Register Select Setup Time to Chip Enable
Register Select Hold Time to Chip Enable
Rising Clock Edge to Falling
Chip Enable Edge
Chip Enable Setup Time to Rising Clock Edge
Chip Enable Hold Time to Rising Clock Edge
Data Setup Time to Rising Clock Edge
Data Hold Time after Rising Clock Edge
Rising Clock Edge to D
OUT[1]
Propagation Delay D
IN
to D
OUT
Simultaneous Mode for One IC
[1,2]
CE Falling Edge to D
OUT
Valid
Clock High Time
Clock Low Time
Reset Low Time
Clock Frequency Frequency
Internal Display Oscillator
Internal Refresh Frequency
External Display Oscillator
Prescaler = 1
Prescaler = 8
t
rss
t
rsh
t
clkce
t
ces
t
ceh
t
ds
t
dh
t
dout
t
doutp
t
cedo
t
clkh
t
clkl
t
rstl
F
cyc
F
inosc
F
rf
F
exosc
4.5 V < V
LOGIC
<5.5 V
Min.
Max.
10
10
20
35
20
10
10
10
40
18
25
80
80
50
5
80
150
51.2
410
210
410
1000
8000
V
LOGIC
= 3 V
Min.
Max.
10
10
20
55
20
10
10
10
65
30
45
100
100
50
4
80
150
51.2
410
210
400
1000
8000
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
KHz
Hz
KHz
KHz
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
7
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
