Receiver Electrical Characteristics
(T
C
= 0 °C to +80 °C, V
CC
= 3.3 V ± 5%, Typical T
C
= +40 °C, V
CC
= 3.3 V)
Parameter
Supply Current
Power Dissipation
Differential Output Impedance
Data Output Differential Peak-to-Peak
Voltage Swing
Inter-channel Skew
Differential Data Output Rise/Fall Time
Signal Detect Assert Time (OFF-to-ON)
De-assert Time (ON-to-OFF)
Control I/O
Output Voltage Low
LVTTL & LVCMOS Output Voltage High
Compatible
Symbol
I
CCR
P
DISR
Z
OUT
DV
DOUTP-P
Min.
Typ.
400
1.3
Max.
445
1.55
120
750
Unit
mA
W
W
mV
P-P
ps
ps
µs
µs
Reference
(Conditions)
1, Fig. 5
80
450
100
600
2, Fig. 8, 10
3, Figs. 7, 8
100
t
r
/t
f
t
SDA
t
SDD
V
OL
V
OH
V
EE
2.5
110
170
190
150
150
4
5
6
7
(I
OL
= 4.0 mA)
(I
OH
= -0.5 mA)
3.1
0.4
V
CC
V
V
Notes:
1. I
CC
R is the dc supply current, dependent upon the number of active channels, where the Data Outputs are ac coupled with capacitors between the
outputs and any resistive terminations. See Figure 7 for recommended termination.
2. Measured over the range 4 MHz to 2 GHz.
3.
DV
DOUTP-P
=
DV
DOUTH
–
DV
DOUTL
, where
DV
DOUTH
= High State Differential Data Output Voltage and
DV
DOUTL
= Low State Differential Data Output
Voltage.
DV
DOUTH
and
DV
DOUTL
= V
DOUT+
– V
DOUT–
, measured with a 100
W
differential load connected with the recommended coupling capacitors
and with a 2500 MBd, 8B10B serial encoded data pattern.
4. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals. Input power at –10 dBm.
5. Rise and Fall Times are measured between the 20% and 80% levels using a 500 MHz square wave signal.
6. The Signal Detect output will change from logic “0” (Low) to “1” (High) within the specified assert time for a step transition in optical input power
from the de-asserted condition to the specified asserted optical power level on all 12 channels.
7. The Signal Detect output will change from logic “1” (High) to “0” (Low) within the specified de-assert time for a step transition in optical input
power from the specified asserted optical power level to the de-asserted condition on any 1 channel.
7
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
