HSDL - 7002
IrDA
3/16 Encode/Decode
Integrated Circuit in QFN Package
Data Sheet
Description
The HSDL-7002 modulates and demodulates electrical
pulses from HSDL-3201 IrDA
transceiver module and
other IrDA
compliant transceivers. The HSDL-7002 can
be used with a microcontroller/microprocessor that has
a serial communication interface (UART).
Prior to communication, the processor selects the transmis-
sion baud rate. Serial data is then transmitted or received
at the prescribed data rate.
The HSDL-7002 consists or two state machines – the SIR
(Serial InfraRed) Encode and SIR Decode blocks. It also
contains a sequential block Clock Divide that synthesizes
the required internal signal.
The HSDL-7002 can be placed into the Internal Clock Mode
or External Clock Mode. An external crystal is needed for
the Internal Clock Mode. In applications where the external
16XCLK signal is provided, a crystal is not needed.
There are two data transmission modes. Data can be trans-
mitter and received in either a standard 3/16 modulation
mode or a 1.63 µs pulse mode.
Features
•
Fully Compliant to IrDA
Physical Layer Specification
1.4 from 9.6 kbit/s to 115.2 kbit/s (SIR)
•
Interfaces with IrDA
Compliant IR Transceiver
•
Miniature Module Size with 16-pin Quad-Flat-No Lead
(QFN) Package
Height : 0.8 mm
Length : 4.0 mm
Depth : 4.0 mm
•
Used in Conjunction with Standard 16550 UART
•
Transmits/Receives either 1.63 µs or 3/16 Pulse Mode
•
Internal or External Clock Mode
•
Programmable Baud Rate
2.7 – 5.5 V Operation
•
Lead Free and Green Product
Applications
•
Interfaces with IrDA
Transceiver in:
•
Telecom Applications:
Mobile Phones
Modems
Pagers
Fax Machines
•
Computer Applications:
Notebook Computers
Desktop PCs
Dongles or other RS-232 adapters
PDAs
Printers
•
Handheld Data Collection:
Industrial
Medical
•
Transportation
/TXD
IR_TXD
/NRST
SIR
Encode
SIR
Decode
/IR_RXD
RXD
HSDL-7002
A0
A1
A2
16XCLK
PULSEMOD
CLK_SEL
Clock
Divide
Figure 1. Block Diagram of HSDL-7002
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
