典型特征
�½ll t�½�½�½ical value�½ are at �½
�½
= �½�½�½C�½�½ �½
CC
= �½ �½�½�½ �½
�½(�½N)
= �½ m�½ unle�½�½ otherwi�½e �½�½ecified.
参数
�½n�½ut Current �½�½�½�½�½tere�½i�½
�½n�½ut Diode �½em�½erature
系数
�½e�½i�½tance (�½n�½ut�½�½ut�½ut)
Ca�½acitance (�½n�½ut�½�½ut�½ut)
�½n�½ut Ca�½acitance
�½ut�½ut �½i�½e �½ime (�½0�½90%)
�½ut�½ut �½all �½ime (90�½�½0%)
符号
�½
�½�½YS
D�½
�½
D�½
�½
�½
�½�½�½
C
�½�½�½
C
�½N
t
r
t
�½
测试条件
�½
CC
= �½ �½
�½
�½
= �½ m�½
�½
�½�½�½
= �½00 �½dc
�½ = �½ M�½�½z
�½
�½
= 0 �½�½�½ �½ = �½ M�½�½z
典型值。
0.07
�½�½.�½�½
�½0
�½�½
�½.0
�½0
�½�½�½
�½0
单位
m�½
m�½�½�½C
W
�½�½
�½�½
n�½
n�½
图。
�½
笔记
�½
�½
�½�½�½ �½
�½�½�½ �½
�½�½�½ �½0
�½�½�½ 7
�½�½�½ 7
�½
�½
单通道产品只
�½ut�½ut Enable �½ime to �½ogic �½�½igh
�½ut�½ut Enable �½ime to �½ogic �½ow
�½ut�½ut Di�½able �½ime �½rom �½ogic �½�½igh
�½ut�½ut Di�½able �½ime �½rom �½ogic �½ow
t
PZ�½�½
t
PZ�½
t
P�½�½Z
t
P�½Z
�½0
�½0
�½�½�½
�½�½
n�½
n�½
n�½
n�½
�½
�½
�½
�½
多通道产品仅
�½n�½ut�½�½n�½ut �½n�½ulation �½eakage
当前
�½e�½i�½tance (�½n�½ut�½�½n�½ut)
Ca�½acitance (�½n�½ut�½�½n�½ut)
�½
�½�½�½
�½
�½�½�½
C
�½�½�½
�½�½�½ ≤ 6�½%�½�½
�½
�½�½�½
= �½00 �½�½�½ t = �½ �½
�½
�½�½�½
= �½00 �½
�½ = �½ M�½�½z
0.�½
�½0
�½�½
�½.�½
n�½
W
�½�½
9
9
9
Note�½�½�½
�½. Peak �½orward �½n�½ut Current �½ul�½e width < �½0 �½�½ at �½ �½�½�½z ma�½imum re�½etition rate.
�½. Each channel o�½ a multichannel device.
�½. Duration o�½ out�½ut �½hort circuit time not to e�½ceed �½0 m�½.
�½�½. �½ll device�½ are con�½idered two�½terminal device�½�½�½ mea�½ured between all in�½ut lead�½ or terminal�½ �½horted together and all out�½ut lead�½ or ter�½
minal�½ �½horted together.
�½. �½hi�½ i�½ a momentar�½�½ with�½tand te�½t�½�½ not an o�½erating condition.
6. CM
�½
i�½ the ma�½imum rate o�½ ri�½e o�½ the common mode voltage that can be �½u�½tained with the out�½ut voltage in the logic low �½tate (�½
�½
< 0.�½
�½). CM
�½�½
i�½ the ma�½imum rate o�½ �½all o�½ the common mode voltage that can be �½u�½tained with the out�½ut voltage in the logic high �½tate (�½
�½
�½�½
�½.0 �½).
7. t
P�½�½�½
�½ro�½agation dela�½�½ i�½ mea�½ured �½rom the �½0% �½oint on the leading edge o�½ the in�½ut �½ul�½e to the �½.�½ �½ �½oint on the leading edge o�½ the
out�½ut �½ul�½e. �½he t
P�½�½�½
�½ro�½agation dela�½�½ i�½ mea�½ured �½rom the �½0% �½oint on the trailing edge o�½ the in�½ut �½ul�½e to the �½.�½ �½ �½oint on the
trailing edge o�½ the out�½ut �½ul�½e.
�½. Mea�½ured between each in�½ut �½air �½horted together and all out�½ut connection�½ �½or that channel �½horted together.
9. Mea�½ured between adjacent in�½ut �½air�½ �½horted together �½or each multichannel device.
�½0. Zero�½bia�½ ca�½acitance mea�½ured between the �½ED anode and cathode.
�½�½. Standard �½art�½ receive �½00% te�½ting at �½�½�½C (Subgrou�½�½ �½ and 9). SMD�½�½ Cla�½�½ �½�½ and Cla�½�½ �½ �½art�½ receive �½00% te�½ting at �½�½�½�½ �½�½�½�½�½ and –�½�½�½C
(Subgrou�½�½ �½ and 9�½�½ �½ and �½0�½�½ �½ and �½�½�½�½ re�½�½ectivel�½�½).
�½�½. Parameter�½ are te�½ted a�½ �½art o�½ device initial characterization and a�½ter de�½ign and �½roce�½�½ change�½. Parameter�½ guaranteed to limit�½ �½�½eci�½
fied �½or all lot�½ not �½�½ecificall�½�½ te�½ted.
10
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
