AL5DAxxxx
3.3V, 5V Asynchronous Dual-Port SRAM
1k/2k/4K/8K/16K/32K x 8/9/16/18-bit
Features
!
True dual port memory cells up to 256/288Kb
!
Fully asynchronous dual-port SRAM aimed at communications market
!
Max. access time: 30 ns
!
Separate upper byte and lower byte control for multiplexed bus compatibility (only for 16/18 bit
devices)
!
Supports byte write/read for 16/18 bit devices
!
On-chip arbitration logic support 3 modes: Busy, Interrupt and Semaphore
-
Busy scheme circuit arbitrate between 2 ports
-
interrupt mechanism allow port to port communication
-
Full hardware support of semaphore to permit software handshaking between ports
!
Versatile pin select for Master or Slave mode:
M/ S
=
V
IH
for
BUSY
output flag on master;
M/ S
=
V
IL
for
BUSY
input flag on slave
!
Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one
device
!
Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)
!
3.3v and 5v series low power respectively
!
Compatible and functionally equivalent to IDT or Cypress
!
Available in 52-PLCC, 68-PLCC, 84-PLCC, 64-TQFP/STQFP, 80-TQFP, 100-TQFP
Architecture
IO
8/9L-15/17L
IO
0L - 7/8L
IO
8/9L -15/17R
IO
0R - 7/8R
A
10L - 14L
A
A
10R -14R
A
0L - 9L
0R - 9R
CE
L
CE
R
OE
L
UB
L
LB
L
OE
R
UB
R
LB
R
R/ W
L
(
1
,
2
)
BUSY
L
SEM
L
(
2
)
INT
L
R/ W
R
(
1
,
2
)
BUSY
R
SEM
R
(
2
)
INT
R
M/ S
©2003 -Copyright by AverLogic Technologies, Corp.
1-F-PMK008-0001
AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
