@vic
AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
SYMBOL
D
(MAX)
D
(MIN)
PARAMETER
Maximum Duty Cycle
Minimum Duty Cycle
TEST CONDITIONS
MIN
95
TYP
97
MAX
100
0
UNIT
%
%
Total Standby Current
Start-up Current
I
ST
Operating Supply Current
I
CC(opr)
Vpin 2=Vpin 3=0V
Vcc Zener Voltage
Vz
Icc=25mA
note 2:These parameters, although guaranteed ,are not 100% tested in production.
note 3:Parameters measured at trip point of latch with Vpin 2=0.
note 4:Gain defined as:
0.12
11
34
0.3
17
mA
mA
V
A=
∆Vpin
1
∆Vpin
3
; 0<=Vpin3<=0.8V
note 5:Adjust Vcc above the start threshold before setting at 15V.
OPEN-LOOP LABORATORY TEST FIXTURE
Vref
4.7kΩ
RT
100kΩ
0.1
µF
1
2
8
7
6
A
0.1
µF
Vcc
Error Amp
Adjust
4.7kΩ
Isense
Adjust
1kΩ
/ 1W
OUTPUT
3
5kΩ
4
CT
5
High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used
to sample the oscillator waveform and apply an adjustable Ramp to Pin 3.
UNDER-VOLTAGE LOCKOUT
Icc
Vcc
<15mA
7
ON/OFF Command
to rest of IC
Von=16V
Voff=10V
<1mA
Voff
Von
Vcc
During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to
GND with a bleeder resistor to prevent activating the power switch with output leakage currents.
QW-R103-002,B
AVICTEK [ Avic Technology ]
