ED050SC3
7.Power on Sequence
1. VSS
2.
VEE
VDD
VNEG
VPOS (Source driver)
VGG(Gate driver)
Power on sequence’s timing chart as blew :
V
GG
V
POS
T1
T2
T3
T4
T5
T6
T7
V
DD
VSS
V
EE
V
NEG
Logic signal input
T1: 100 µs(min)
T2: 0µs(min)
T3: 1000µs (min)
T4: 0 µs ( min)
T5: 0 µs (min)
T6: 0 µs (min)
T7: 0 µs (min)
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