Doc No.:
Issued Date:Dec.15,2006
Model No.: G150X1-L02
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
DCLK
Item
Pixel Clock
Vertical Total Time
Vertical Address Time
Horizontal Total Time
Horizontal Address Time
Symbol
1/TC
TV
TVD
TH
Min.
-
780
768
1140
1024
Typ.
65
806
768
1344
1024
Max.
80
1200
768
1600
1024
Unit
MHz
TH
TH
TC
Note
-
-
-
-
-
DE
THD
TC
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
Tv
DE
TH
DCLK
TC
THD
DE
DATA
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