AZ10EL16VO
AZ100EL16VO
AZ10EL16VOD
AZ100EL16VOD
AZ10EL16VOT
AZ100EL16VOT
AZ10EL16VOU
AZ100EL16VOU
VCC
QHG
QHG
VEE
EN
Q
1
10
9
1
2
3
4
VCC
QHG
8
7
6
5
Q
Q
D
2
3
D
8
TSSOP 8
SOIC 8
TSSOP 10
QHG
VEE
V
BB / D
4
5
7
D
EN
VBB
6
AZ100EL16VON
AZ100EL16VONB
MLP 8, 2x2mm
MLP 8, 2x2mm
D
1
2
3
Q
1
2
3
8
7
VCC
QHG
QHG
Q
D
8
VBB / D
VCC
QHG
QHG
7
VBB / D
6
5
6
5
EN
VEE
VEE
4
EN
4
TOP VIEW
TOP VIEW
MLP 8: Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
AZ10/100EL16VOL
VCC
13
Q
Q
NC
14
MLP 16 (L) Package and DIE:
10K/100K Selection
15
16
1
NC
NC
QHG
QHG
NC
12
Connect pin/pad 10K to VEE to select
10K operation. Float (NC) pin/pad 10K
to select 100K operation. VEE
MLP 16,
3x3 mm
2
3
11
10
9
D
D
connection must be less than 1Ω.
Pin 6 of the MLP 16 package may be
connected to pin 7 (VEE) with no effect
on the circuit.
VBB
4
5
6
8
7
VEE
EN
NC
10K
MPL 16: Bottom Center Pad may be left
open or tied to VEE. Pin 7 is the VEE return.
June 2007 * REV - 23
www.azmicrotek.com
11