欢迎访问ic37.com |
会员登录 免费注册
发布采购

AZ10EL32T 参数 Datasheet PDF下载

AZ10EL32T图片预览
型号: AZ10EL32T
PDF下载: 下载PDF文件 查看货源
内容描述: ECL / PECL ÷ 2分频器 [ECL/PECL ± 2 Divider]
分类和应用:
文件页数/大小: 6 页 / 104 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
 浏览型号AZ10EL32T的Datasheet PDF文件第2页浏览型号AZ10EL32T的Datasheet PDF文件第3页浏览型号AZ10EL32T的Datasheet PDF文件第4页浏览型号AZ10EL32T的Datasheet PDF文件第5页浏览型号AZ10EL32T的Datasheet PDF文件第6页  
ARIZONA MICROTEK, INC.
AZ10EL32
AZ100EL32
FEATURES
PACKAGE
510ps Propagation Delay
3.0GHz Toggle Frequency
High Bandwidth Output Transitions
75kΩ Internal Input Pulldown Resistors
Direct Replacement for ON
Semiconductor MC10EL32 &
MC100EL32
SOIC 8
SOIC 8
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
TSSOP 8
TSSOP 8
1
2
ECL/PECL
÷
2 Divider
PACKAGE AVAILABILITY
PART NUMBER
AZ10EL32D
AZ100EL32D
AZ100EL32D+
AZ10EL32T
AZ100LVEL32T
MARKING
AZM10
EL32
AZM100
EL32
AZM100+
EL32
AZT
EL32
AZH
EL32
NOTES
1,2
1,2
1,2
1,2
1,2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
DESCRIPTION
The AZ10/100EL32 is an integrated
÷2
divider. The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of
multiple EL32’s in a system.
The EL32 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the device. For
single-ended input applications, the V
BB
reference should be connected to one side of the CLK/CLK differential input
¯¯¯¯
pair. The input signal is then fed to the other CLK/CLK input. The V
BB
pin should be used only as a bias for the
¯¯¯¯
EL32 as its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a 0.01μF
capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
RESET 1
8
V
CC
PIN DESCRIPTION
PIN
CLK, CLK
¯¯¯
RESET
V
BB
Q, Q
¯
V
CC
V
EE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
R
CLK
2
÷2
CLK
3
6
Q
7
Q
V
BB
4
5
V
EE
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com