ARIZONA MICROTEK, INC.
AZ10ELT22
AZ100ELT22
CMOS/TTL to Differential PECL Translator
FEATURES
Green / RoHS Compliant /
Lead (Pb) Free package available
•
0.5ns Typical Propagation Delay
•
<100ps Typical Output to Output
Skew
•
Differential PECL Outputs
•
Flow Through Pinouts
•
Operating Range of 3.0V to 5.5V
•
Direct Replacement for
ON Semiconductor MC10ELT22 &
MC100ELT22
•
IBIS Model Files Available on
Arizona Microtek Website
•
PACKAGE
SOIC 8
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
SOIC 8
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
TSSOP 8
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
TSSOP 8
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
1
PACKAGE AVAILABILITY
PART NUMBER
AZ10ELT22D
AZ10ELT22D+
AZ100ELT22D
AZ100ELT22D+
AZ10ELT22T
AZ10ELT22T+
AZ100ELT22T
AZ100ELT22T+
MARKING
AZM10
ELT22
AZM10+
ELT22
AZM100
ELT22
AZM100+
ELT22
AZT
LT22
AZT+
LT22
AZH
LT22
AZH+
LT22
NOTES
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
DESCRIPTION
2
The AZ10/100ELT22 is a dual
3
CMOS/TTL to differential PECL
4
translator. Because PECL (Positive ECL)
levels are used, only V
CC
and ground are
required. The small outline packaging and the low skew, dual gate design of the ELT22 makes it ideal for
applications that require the translation of a clock and a data signal.
The ELT22 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while
the 100ELT is compatible with PECL 100K logic levels.
NOTE: Specifications in PECL tables are valid when thermal equilibrium is established.
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Parts marked JNB for date codes prior to 4WW (prior to 2004).
Date code “YWW” or “YYWW” on underside of part.
LOGIC DIAGRAM AND
PINOUT
PIN DESCRIPTION
PIN
Q0, Q0, Q1, Q1
¯¯
¯¯
D0, D1
V
CC
GND
FUNCTION
Differential PECL Outputs
CMOS/TTL Input
Positive Supply
Ground
1630 S. STAPLEY DR., SUITE 127
•
MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (480) 890-2541
www.azmicrotek.com