ARIZONA MICROTEK, INC.
AZ100LVEL16VR
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
•
•
•
•
•
•
•
•
Green and RoHS Compliant /
Lead (Pb) Free Packages Available
Enhanced Enable Operation
High Bandwidth for
≥1GHz
Similar Operation as AZ100EL16VO
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a MLP 16 or MLP 8
Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
PACKAGE
MLP 16 (3x3)
MLP 16 (3x3) RoHS
Compliant / Lead
(Pb) Free
MLP 8 (2x2) Green /
RoHS Compliant /
Lead (Pb) Free
DIE
1
2
3
PACKAGE AVAILABILITY
PART NO.
AZ100LVEL16VRL
AZ100LVEL16VRL+
AZ100LVEL16VRNEG
AZ100LVEL16VRX
MARKING
AZM
16R
<Date Code>
AZM+
16R
<Date Code>
R5G
<Date Code>
N/A
NOTES
1,2
1,2
1,2
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack
DESCRIPTION
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable
function. The Q
HG
/Q
HG
outputs have voltage gain several times greater than the Q/Q outputs.
¯
¯
MLP 16, 3x3 mm Package (VRL) or DIE (VRX)
The AZ100LVEL16VR provides a selectable Q
HG
/Q
HG
enable that allows continuous oscillator operation via
¯
the Q/Q outputs. The enable truth table on the next page shows the operating modes. Leaving EN-SEL open (NC)
¯
selects PECL/ECL operation for the EN pad/pin. In this mode the Q
HG
/Q
HG
outputs are enabled when EN is left
¯
open (NC) or set to a PECL/ECL low.
Connecting EN-SEL to V
CC
, V
EE
or V
BB
selects CMOS operation for the EN pad/pin. When EN-SEL is tied to
V
EE
, the Q
HG
/Q
HG
outputs are disabled when EN is left open (NC). When EN-SEL is tied to V
CC
or V
BB
, the Q
HG
/Q
¯
¯
1
HG
outputs are enabled when EN is left open. This default logic condition can be overridden by a
≤20kΩ
resistor
connected to the opposite supply.
The AZ100LVEL16VR also provides a V
BB
and 470Ω internal bias resistors from D to V
BB
and D to V
BB
. The
¯
V
BB
pin supports 1.5mA sink/source current. V
BB
should be bypassed to ground or V
CC
with a 0.01
μF
capacitor.
Outputs Q/Q each have a selectable on-chip pull-down current source. See the current source truth table on the
¯
next page for the supported values. External resistors may also be used to increase pull-down current to a maximum
total of 25mA for the Q/Q outputs.
¯
Each of the Q
HG
/Q
HG
outputs has an optional on-chip pull-down current source of 10 mA. When pad/pin V
EEP
is
¯
left open (NC), the output current sources are disabled and the Q
HG
/Q
HG
operate as standard PECL/ECL. When V
EEP
¯
is connected to V
EE
, the current sources are activated. The Q
HG
/Q
HG
pull-down current can be decreased by using a
¯
resistor between V
EEP
and V
EE
.
This operational mode (EN-SEL to V
CC
or V
BB
) is not supported for date codes prior to 0428 (July 2004). EN-SEL to V
EE
is supported for all
date codes.
1
1630 S. STAPLEY DR., SUITE 127
•
MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
