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AZ100LVEL16VVXP 参数 Datasheet PDF下载

AZ100LVEL16VVXP图片预览
型号: AZ100LVEL16VVXP
PDF下载: 下载PDF文件 查看货源
内容描述: 双频ECL / PECL振荡器增益级和缓冲区启用 [Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable]
分类和应用: 振荡器
文件页数/大小: 9 页 / 94 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
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ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
High Bandwidth for
≥1GHz
Similar Operation as AZ100EL16VR
except with selectable data input pairs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Available in a 3x3mm MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE
MLP 16 (3x3) RoHS
Compliant / Lead (Pb)
Free
DIE
1
2
3
PACKAGE AVAILABILITY
PART NUMBER
AZ100LVEL16VVL+
AZ100LVEL16VVXP
MARKING
AZM+
16K
<Date Code>
N/A
NOTES
1,2
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The Q
HG
/Q
HG
outputs have a voltage gain several times greater than the Q/Q
¯
¯
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D0 is selected. When the
¯¯
SEL pin is HIGH data from the D1/D1 is selected. Allowing continuous oscillator operation, the (EN) enable works
¯¯
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the Q
HG
/Q
HG
outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
¯
the Q/Q outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
¯
type logic signal.
The AZ100LVEL16VV also provides a V
BB
with a 1.5mA sink/source current. Each data input is separately
connected to V
BB
with a 470Ω internal bias resistor. Bypassing V
BB
to ground with a 0.01
μF
capacitor is
recommended.
Each Q/Q output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
¯
pull-down current of the Q/Q to a maximum of 25mA each (includes a 4 mA on-chip current source).
¯
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com