欢迎访问ic37.com |
会员登录 免费注册
发布采购

AZ100LVEL33TG 参数 Datasheet PDF下载

AZ100LVEL33TG图片预览
型号: AZ100LVEL33TG
PDF下载: 下载PDF文件 查看货源
内容描述: ECL / PECL ± 4分频器 [ECL/PECL ÷4 Divider]
分类和应用:
文件页数/大小: 8 页 / 107 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
 浏览型号AZ100LVEL33TG的Datasheet PDF文件第2页浏览型号AZ100LVEL33TG的Datasheet PDF文件第3页浏览型号AZ100LVEL33TG的Datasheet PDF文件第4页浏览型号AZ100LVEL33TG的Datasheet PDF文件第5页浏览型号AZ100LVEL33TG的Datasheet PDF文件第6页浏览型号AZ100LVEL33TG的Datasheet PDF文件第7页浏览型号AZ100LVEL33TG的Datasheet PDF文件第8页  
ARIZONA MICROTEK, INC.
AZ100LVEL33
ECL/PECL
÷4
Divider
FEATURES
PACKAGE
Green / RoHS Compliant /
Lead (Pb) Free package available
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
5.0+ GHz Toggle Frequency
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC100EL33 & MC100LVEL33
Transistor Count = 91 Devices
IBIS Model Files Available on Arizona
Microtek Web Site
>2 kV HBM ESD Protection
Additional ESD Data Available on
Arizona Microtek Website
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
MSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
1
2
3
PACKAGE AVAILABILITY
PART NUMBER
AZ100LVEL33NG
MARKING
C3G
<Date Code>
AZM100G
LVEL33
AZHG
LV33
NOTES
1,2
AZ100LVEL33DG
1,2,3
AZ100LVEL33TG
1,2,3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Date code “YWW” or “YYWW” on underside of part.
DESCRIPTION
The AZ100LVEL33 is an integrated
÷4
divider. The RESET pin is asynchronous and clears the output (Q Low,
Q High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for
¯
the synchronization of multiple LVEL33’s in a system.
The LVEL33 provides a V
BB
output for single-end use or a DC bias reference for AC coupling to the device.
¯¯¯¯
For single-ended input applications, the V
BB
reference should be connected to one side of the CLK/ CLK differential
input pair. The input signal is then fed to the other CLK/ CLK input. The V
BB
pin can support 1.0mA sink/source
¯¯¯¯
current. When used, the V
BB
pin should be bypassed to ground via a 0.01F capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM
PIN DESCRIPTION
PIN
CLK, CLK
¯¯¯
RESET
V
BB
Q, Q
¯
V
CC
V
EE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
RESET
R
Q
÷4
CLK
CLK
V
BB
Q
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (623) 505-2414
www.azmicrotek.com