ARIZONA MICROTEK, INC.
AZ10ELT20
AZ100ELT20
CMOS/TTL to Differential PECL Translator
FEATURES
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PACKAGE
0.5ns Typical Propagation Delay
Differential PECL Outputs
Flow Through Pinouts
Operating Range of +3.0V to +5.5V
Direct Replacement for ON Semi
MC10ELT20, MC100ELT20,
MC100LVELT20 & Micrel
SY89329V
Available in 2x2 and 3x3 mm MLP
Packages
IBIS Model Files Available on
Arizona Microtek Website
MLP 8 (2x2x0.75)
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead
(Pb) Free
MLP 16 (3x3)
Green / RoHS
Compliant / Lead
(Pb) Free
SOIC 8
SOIC 8
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
TSSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
DIE
1
2
PACKAGE AVAILABILITY
PART NUMBER
AZ100ELT20N
MARKING
TC
<Date Code>
TCG
<Date Code>
AZMG
T20
<Date Code>
AZM10
ELT20
AZM100
ELT20
AZM100G
ELT20
AZHG
LT20
N/A
NOTES
1,2
AZ100ELT20NG
1,2
AZ10/100ELT20LG
1,2
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AZ10ELT20D
AZ100ELT20D
AZ100ELT20DG
1,2,3
1,2,3
1,2,3
AZ100ELT20TG
AZ10/100ELT20XP
1,2,3
4
DESCRIPTION
3
The
AZ10/100ELT20
is
a
4
CMOS/TTL to differential PECL
translator. It operates with a single power
supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications. The
extremely small MLP 8 2x2 mm package makes it ideal for those applications where space, performance and low
power are at a premium.
When the D input is left floating, the Q output is forced HIGH, and the Q output is forced LOW.
¯
The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels
while the AZ100ELT20 is compatible with PECL 100K logic levels.
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Date code “YWW” or “YYWW” on underside of part.
Waffle Pack.
NOTE: Specifications in the PECL tables are valid when thermal equilibrium is established.
BLOCK DIAGRAM
Q
D
Q
1630 S. STAPLEY DR., SUITE 127
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MESA, ARIZONA 85204
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USA
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(480) 962-5881
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FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
