ARIZONA MICROTEK, INC.
AZ10LVEL32
AZ100LVEL32
FEATURES
•
•
•
•
•
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
3.0GHz Toggle Frequency
High Bandwidth Output Transitions
Direct Replacement for ON
Semiconductor MC10EL/LVEL32 &
MC100EL/LVEL32
PACKAGE
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
TSSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
1
2
3
ECL/PECL
÷
2 Divider
PACKAGE AVAILABILITY
PART NUMBER
AZ100LVEL32DG
AZ100LVEL32TG
AZ100LVEL32NG
MARKING
AZM100G
LVEL32
AZHG
LV32
C2G
<Date Code>
NOTES
1,2
1,2
1,3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
Date code format: “Y” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100LVEL32 is an integrated
÷2
divider. The reset pin is asynchronous and is asserted on the rising
edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization
of multiple LVEL32’s in a system.
The LVEL32 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V
BB
reference should be connected to one side of the CLK/CLK differential
¯¯¯¯
input pair. The input signal is then fed to the other CLK/CLK input. The V
BB
pin should be used only as a bias for
¯¯¯¯
the LVEL32 as its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a
0.01μF capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
RESET 1
8
V
CC
PIN
CLK, CLK
¯¯¯
RESET
V
BB
Q, Q
¯
V
CC
V
EE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
R
CLK
2
÷2
CLK
3
6
Q
7
Q
V
BB
4
5
V
EE
1630 S. STAPLEY DR., SUITE 127
•
MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (623) 505-2414
www.azmicrotek.com