ARIZONA MICROTEK, INC.
AZP92
ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable
FEATURES
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•
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Green and RoHS Compliant / Lead (Pb)
Free Package Available
3.0V to 5.5V Operation
Selectable Divide Ratio
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Selectable Input Biasing
High Bandwidth for
≥1GHz
Available in a MLP 8 (2x2) Package
IBIS Model File Available on Arizona
Microtek Website
PACKAGE
MLP 8 (2x2) Green
/ RoHS Compliant
/ Lead (Pb) Free
DIE
1
2
3
4
PACKAGE AVAILABILITY
PART NO.
AZP92NAG
AZP92X
MARKING
P1G
<Date Code>
N/A
NOTES
1,2
3,4
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack
Contact factory for availability
DESCRIPTION
The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If
DIV-SEL is connected to V
EE
, it functions as a ÷2 divider.
A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN)
functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), V
EE
, or connected to V
EE
via a 20kΩ resistor. Leaving EN-SEL open or connecting it to V
EE
will select the EN pin/pad to function as an active
high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the
outputs whenever EN is left open. When EN-SEL is connected to V
EE
, an internal 75kΩ pull-down resistor is
selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to V
EE
with a 20kΩ resistor will select the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). This default logic condition can be overridden by connecting the EN to V
CC
with an external resistor of
≤20kΩ.
Refer to the enable truth table on the next page for detailed operation.
DIE (AZP92X)
¯
The AZP92X provides a V
BB
and a BIAS pad with 940Ω internal resistors from D to BIAS and D to BIAS.
Connecting the BIAS pad to V
BB
allows D and D to be AC coupled with minimal external components. For single
¯
ended applications, D or D may be connected directly to V
BB
to form a single 1880Ω bias resistor. The V
BB
pin
¯
supports 1.5mA sink/source current. Whenever used, the V
BB
should be bypassed to ground or V
CC
with a 0.01
μF
capacitor.
MLP 8, 2x2 mm Package (AZP92NA)
The AZP92NA provides a V
BB
with an 1880Ω internal bias resistor from D to V
BB
. This feature allows AC
coupling with minimal external components. The V
BB
pin supports 1.5mA sink/source current and should be
bypassed to ground or V
CC
with a 0.01
μF
capacitor.
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
1630 S. STAPLEY DR., SUITE 127
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MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
