ADS1230
www.ti.com
SBAS366–OCTOBER 2006
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(Top View)
DVDD
DGND
CLKIN
GAIN
CAP
1
2
3
4
5
6
7
8
16 DRDY/DOUT
15 SCLK
14 PDWN
13 SPEED
12 AVDD
11 AGND
10 REFP
ADS1230
CAP
AINP
AINN
9
REFN
PIN DESCRIPTIONS
ANALOG/DIGITAL
INPUT/OUTPUT
NAME
TERMINAL
DESCRIPTION
DVDD
DGND
CLKIN
1
2
3
Digital
Digital
Digital Power Supply: 2.7V to 5.3V
Digital Ground
Digital/Digital Input
External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator.
PGA Gain Select
GAIN
PGA
64
GAIN
4
Digital Input
0
1
128
CAP
5
6
Analog
Analog
Gain Amp Bypass Capacitor Connection
Gain Amp Bypass Capacitor Connection
Positive Analog Input
CAP
AINP
AINN
REFN
REFP
AGND
AVDD
7
Analog Input
Analog Input
Analog Input
Analog Input
Analog
8
Negative Analog Input
9
Negative Reference Input
Positive Reference Input
Analog Ground
10
11
12
Analog
Analog Power Supply, 2.7V to 5.3V
Data Rate Select:
SPEED
DATA RATE
SPEED
13
Digital Input
0
1
10SPS
80SPS
PDWN
SCLK
14
15
Digital Input
Digital Input
Power-Down: Holding this pin low powers down the entire converter and resets the ADC.
Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep
modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections
for more details.
Dual-Purpose Output:
DRDY/DOUT
16
Digital Output
Data Ready: Indicates valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge of SCLK.
5
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