ADS1255
ADS1256
www.ti.com
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
CS
t
3
SCLK
t
4
DIN
t
7
DOUT
t
8
t
9
t
5
t
6
t
2L
t
11
t
1
t
2H
t
10
Figure 1. Serial Interface Timing
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL
t1
t2H
t2L
t3
t4
t5
t6
t7
t8
t9
t10
DESCRIPTION
SCLK period
200
SCLK pulse width: high
SCLK pulse width: low
CS low to first SCLK: setup time(3)
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
SCLK rising edge to valid new DOUT: propagation delay(4)
SCLK rising edge to DOUT invalid: hold time
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
CS low after final SCLK falling edge
RREG, WREG, RDATA
t11
Final SCLK falling edge of command to first SCLK
rising edge of next command.
RDATAC, RESET, SYNC
RDATAC, STANDBY, SELFOCAL, SY-
SOCAL, SELFGCAL,
SYSGCAL, SELFCAL
0
6
0
4
24
10
200
0
50
50
50
50
9
MIN
4
10
MAX
UNIT
τ
CLKIN(1)
τ
DATA(2)
ns
τ
DATA
ns
ns
ns
ns
τ
CLKIN
ns
ns
τ
CLKIN
ns
τ
CLKIN
τ
CLKIN
Wait for DRDY to go low
(1)
τ
CLKIN = master clock period = 1/fCLKIN.
(2)
τ
DATA = output data period 1/fDATA.
(3) CS can be tied low.
(4) DOUT load = 20pF
100kΩ to DGND.
6
BURR-BROWN [ BURR-BROWN CORPORATION ]
