The reference current diminishes directly with both conver-
sion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the con-
verter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Perfor-
mance Curves section for more information.
value for one clock period. For the next 12 DCLOCK
periods, D
OUT
will output the conversion result, most sig-
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DIGITAL INTERFACE
SERIAL INTERFACE
The ADS7816 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for D
OUT
is acceptable,
the system can use the falling edge of DCLOCK to capture
each bit.
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
SYMBOL
t
SMPL
t
CONV
t
CYC
t
CSD
t
SUCS
t
hDO
t
dDO
t
dis
t
en
t
f
t
r
DESCRIPTION
Analog Input Sample TIme
Conversion Time
Throughput Rate
CS Falling to
DCLOCK LOW
CS Falling to
DCLOCK Rising
DCLOCK Falling to
Current D
OUT
Not Valid
DCLOCK Falling to Next
D
OUT
Valid
CS Rising to D
OUT
Tri-State
DCLOCK Falling to D
OUT
Enabled
D
OUT
Fall Time
D
OUT
Rise Time
MIN
1.5
TYP
MAX
2.0
UNITS
Clk Cycles
Clk Cycles
kHz
ns
ns
ns
12
200
0
30
15
85
25
50
70
60
150
50
100
100
100
ns
ns
ns
ns
ns
TABLE I. Timing Specifications –40°C to +85°C.
t
CYC
CS/SHDN
t
SUCS
DCLOCK
t
CSD
D
OUT
HI-Z
NULL
BIT
NULL
BIT
POWER
DOWN
HI-Z
B8
B7
B6
B5
B4
B3
B2
B1 B0
(1)
t
SMPL
B11 B10 B9
(MSB)
B11 B10
B9
B8
t
CONV
t
DATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
t
CYC
CS/SHDN
t
SUCS
DCLOCK
t
CSD
D
OUT
HI-Z
NULL
BIT
HI-Z
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
(2)
POWER DOWN
t
SMPL
B11 B10 B9
(MSB)
t
CONV
t
DATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
t
DATA
: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS7816 Basic Timing Diagrams.
®
9
ADS7816
BURR-BROWN [ BURR-BROWN CORPORATION ]
