PIN CONFIGURATION
Top View
SO
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DESIGNATOR
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+V
S
CLK
+V
S
OE
MSBI
DESCRIPTION
Ground
Bit 1, Most Significant Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12, Least Significant Bit
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
output. Internal pull-down resistors.
+5V Power Supply
Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
Complementary Input
Ground
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
1
2
3
4
5
6
7
ADS800
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
IN
IN
GND
+V
S
REFT
CM
REFB
+V
S
MSBI
OE
+V
S
CLK
+V
S
20
21
22
23
24
25
26
27
28
+V
S
REFB
CM
REFT
+V
S
GND
IN
IN
GND
TIMING DIAGRAM
t
CONV
Convert
Clock
Hold
“N”
t
L
t
D
t
H
Internal
Track-and-Hold
Track
DATA LATENCY
(6.5 Clock Cycles)
(1)
Hold
Hold
Hold
Hold
Hold
Hold
Track “N + 1” Track “N + 2” Track “N + 3” Track “N + 4” Track “N + 5” Track “N + 6” Track
t
2
Output
Data
Data Valid
N–8
Data Valid
N–7
Data Valid
N–6
N–5
N–4
N–3
N–2
N–1
N
t
1
Data Invalid
SYMBOL
t
CONV
t
L
t
H
t
D
t
1
t
2
DESCRIPTION
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, C
L
= 0pF
New Data Delay Time, C
L
= 15pF max
MIN
25
12
12
(2)
3.9
TYP
MAX
100µs
UNITS
ns
ns
ns
ns
ns
ns
12.5
12.5
2
12.5
NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
(2) t
H
must be 13ns minimum if no missing codes is desired only for the conditions of t
CONV
≤
28ns
and f
IN
< 2MHz.
4
ADS800
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SBAS035B
BURR-BROWN [ BURR-BROWN CORPORATION ]
