ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= +25°C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS800U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
(Cont.)
2-Tone Intermodulation Distortion (IMD)
(4)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Aperture Delay Time
Aperture Jitter
Over-Voltage Recovery Time
(5)
OUTPUTS
Logic Family
Logic Coding
Logic Levels
NTSC or PAL
NTSC or PAL
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
61
57
61
56
59
54
56
51
–63
–62
64
63
62
62
63
64
58
57
0.5
0.1
2
7
2
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
%
degrees
ns
ps rms
ns
1.5x Full-Scale Input
Logic “LO”,
C
L
= 15pF max
Logic “HI”,
C
L
= 15pF max
Logic Selectable
Full
Full
TTL/HCT Compatible CMOS
SOB or BTC
0
0.4
+2.5
20
2
+4.75
+5.0
78
78
390
390
75
+V
S
40
10
+5.25
93
97
465
485
V
V
ns
ns
V
mA
mA
mW
mW
°C/W
3-State Enable Time
3-State Disable Time
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Supply Current: +I
S
Power Consumption
Thermal Resistance,
θ
JA
SO-28
Operating
Operating
Operating
Operating
Operating
Full
Full
+25°C
Full
+25°C
Full
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
ADS800
SBAS035B
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3
BURR-BROWN [ BURR-BROWN CORPORATION ]
