To operate the DAC715 interface as a single-buffered latch,
the DATA INPUT LATCH is permanently enabled by
connecting A
0
to DCOM. If A
1
is not used to enable the
D/A, it should be connected to DCOM also. For this mode
of operation, the width of WR will need to be at least 80ns
minimum to pass data through the DATA INPUT LATCH
and into the D/A LATCH.
TRANSPARENT INTERFACE
The digital interface of the DAC715 can be made transpar-
ent by asserting A
O
, A
1
, and WR LOW, and asserting CLR
HIGH.
Internal
+10V Reference
V
REF OUT
5
P
1
1kΩ
170Ω
R
1
100Ω
Gain Adjust
6
Offset Adjust
15kΩ
10kΩ
4
R
2
2MΩ
+V
CC
P
2
10kΩ – 100kΩ
5kΩ
R
3
27kΩ
–V
CC
≈
+2.5V
IDAC
0-2mA
2
ACOM
3
+10V V
OUT
For no external adjustments, pins 4 and 6 are not connected.
External resistors R1 - R4 are standard ±1% values. Range of
adjustment at least ±0.03% FSR.
FIGURE 6. Manual Offset and Gain Adjust Circuits.
®
DAC715
10
BURR-BROWN [ BURR-BROWN CORPORATION ]
