TYPICAL CHARACTERISTICS: V
DD
= +2.7V
(Cont.)
At T
A
= +25°C, +V
DD
= +2.7V, unless otherwise noted.
EXITING POWER-DOWN
(800
H
Loaded)
CLK (2.7V/div)
CODE CHANGE GLITCH
Loaded with 2kΩ
and 200pF to GND.
Code Change:
800
H
to 7FF
H
.
V
OUT
(20mV/div)
V
OUT
(1V/div)
Time (5µs/div)
Time (0.5µs/div)
THEORY OF OPERATION
DAC SECTION
The DAC7512 is fabricated using a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Since there is no reference input pin, the
power supply (V
DD
) acts as the reference. Figure 1 shows a
block diagram of the DAC architecture.
V
DD
R
R
R
To Output
Amplifier
DAC Register
REF (+)
Resistor
String
REF(–)
V
OUT
Output
Amplifier
GND
FIGURE 1. DAC7512 Architecture.
R
The input coding to the DAC7512 is straight binary, so the
ideal output voltage is given by:
V
OUT
=
V
DD
•
D
4096
R
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
FIGURE 2. Resistor String.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply
a string of resistors, each of value R. The code loaded into
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by
closing one of the switches connecting the string to the
amplifier. It is tested monotonic because it is a string of
resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-
rail voltages on its output which gives an output range of
0V to V
DD
. It is capable of driving a load of 2kΩ in parallel
with 1000pF to GND. The source and sink capabilities of the
output amplifier can be seen in the typical characteristics.
The slew rate is 1V/µs with a half-scale settling time of 8µs
with the output unloaded.
DAC7512
SBAS156B
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11
BURR-BROWN [ BURR-BROWN CORPORATION ]
