24th Falling
Edge
SCLK
1
2
1
2
24th Falling
Edge
SYNC
Invalid Write-Sync Interrupt:
SYNC HIGH before 24th Falling Edge
DIN
DB23 DB22
DB0
Valid Write -Buffer/DAC Update:
SYNC HIGH after 24th Falling Edge
DB23 DB22
DB1
DB0
FIGURE 4. Interrupt and Valid SYNC Timing.
DB23
0
DB11
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
LDB
LDA
X
Buffer Select
PD1
PD0
D15
D14
D13
DB12
D12
DB0
D0
FIGURE 5. DAC8532 Data Input Register Format.
D23
D22
D21
D20
D19
D18
D17
D16
PD0
D15
MSB
D14
MSB-1
D13-D0
MSB-2...LSB
DESCRIPTION
Reserved Reserved Load B Load A Don’t Care Buffer Select PD1
(Always Write 0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
0 = A, 1 = B
#
#
#
0
1
#
0
1
#
0
1
0
0
Data
X
Data
X
X
Data
X
X
Data
X
X
WR Buffer # w/Data
WR Buffer # w/Power-Down Command
WR Buffer # w/Data and Load DAC A
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
WR Buffer B w/Power-Down Command and LOAD DAC A
WR Buffer # w/Data and Load DAC B
WR Buffer A w/Power-Down Command and LOAD DAC B
WR Buffer B w/ Power-Down Command and LOAD DAC B
(DAC B Powered Down)
WR Buffer # w/Data and Load DACs A and B
WR Buffer A w/Power-Down Command and Load DACs A
and B (DAC A Powered Down)
WR Buffer B w/Power-Down Command and Load DACs A
and B (DAC B Powered Down)
(see Table III)
0
0
(see Table III)
(see Table III)
0
0
(see Table III)
(see Table III)
0
0
(see Table III)
(see Table III)
TABLE II. Control Matrix.
D17
PD1
0
1
1
D16
PD0
1
0
1
1kΩ
100kΩ
High Impedance
OUTPUT IMPEDANCE POWERDOWN COMMANDS
TABLE III. Power-Down Commands.
12
www.ti.com
DAC8532
SBAS246A
BURR-BROWN [ BURR-BROWN CORPORATION ]
