SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1738 requires a system clock for operating the
digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCKI input
(pin 7). The PCM1738 has a system-clock detection circuit
that automatically senses if the system clock is operating at
128f
S
to 768f
S
. Table I shows examples of system-clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator is an excellent choice for providing the
PCM1738 system clock.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 10). SCKO can operate at either full
(f
SCKI
) or half (f
SCKI
/2) rate. The SCKO output frequency
may be programmed using the CLKD bit of Control Regis-
ter 19. The SCKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 19. The default is
SCKO enabled.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1738 includes a power-on reset function (see
Figure 2). The system clock input at SCKI should be active
for at least one clock period prior to V
DD
= 2.0V. With the
system clock active, and V
DD
> 2.0V, the power-on reset
function will be enabled. The initialization sequence re-
quires 1024 system clocks from the time V
DD
> 2.0V. After
the initialization period, the PCM1738 will be set to its reset
default state, as described in the Mode Control Register
section of this data sheet.
The PCM1738 also includes an external reset capability
using the RST input (pin 1). This allows an external control-
ler or master reset circuit to force the PCM1738 to initialize
to its reset default state.
See Figure 3 for external reset operation and timing. The
RST pin is set to a logic “0” for a minimum of 20ns. The
RST pin is then set to a logic “1” state that starts the
initialization sequence that requires 1024 system clock peri-
ods. After the initialization sequence is complete, the
PCM1738 will be set to its reset default state, as described
in the Mode Control Register section of this data sheet.
The external reset is especially useful in applications where
there is a delay between the PCM1738 power-up and system
clock activation. In this case, the RST pin should be held at
a logic “0” level until the system clock has been activated.
The RST pin may then be set to a logic “1” state to start the
initialization sequence.
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
SAMPLING
FREQUENCY
32kHz
44.1kHz
48kHz
96kHz
192kHz
128f
S
4.0960
5.6488
6.1440
12.2880
24.5760
192f
S
6.1440
8.4672
9.2160
18.4320
36.8640
256f
S
8.1920
11.2896
12.2880
24.5760
49.1520
384f
S
12.2880
16.9344
18.4320
36.8640
73.7280
512f
S
16.3840
22.5792
24.5760
49.1520
See Note (1)
768f
S
24.5760
33.8688
36.8640
73.7280
See Note (1)
NOTE: (1) This system clock is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
t
SCKH
“H”
System Clock
“L”
t
SCKL
System clock pulse
cycle time
(1)
0.8V
2.0V
System Clock Pulse Width HIGH t
SCKH
: 5ns (min)
System Clock Pulse Width LOW t
SCKL
: 5ns (min)
FIGURE 1. System Clock Input Timing.
PCM1738
SBAS174B
11
BURR-BROWN [ BURR-BROWN CORPORATION ]
