PIN CONFIGURATION
Top View
TSSOP
Top View
DCLK
CS
DIN
BUSY DOUT
VFBGA
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
1
2
3
4
5
6
7
8
TSC2046
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
+V
CC
B
NC
NC
NC
NC
NC
PENIRQ
C
+V
CC
D
NC
NC
NC
NC
NC
V
REF
E
Y+
F NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AUX
X+
NC
NC
NC
NC
IOVDD
1
A NC
2
3
4
5
6
7
NC
DOUT
PENIRQ
IOVDD
V
REF
G NC
NC
X–
Y–
GND
GND
V
BAT
Top View
15 PENIRQ
TSSOP
14 IOVDD
16 DOUT
BUSY
DIN
CS
DCLK
1
2
TSC2046
3
4
13 V
REF
12
11
10
9
AUX
V
BAT
GND
Y–
5
6
7
Y+
+V
CC
X+
PIN DESCRIPTION
TSSOP PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VFBGA PIN #
B1 and C1
D1
E1
G2
G3
G4 and G5
G6
E7
D7
C7
B7
A6
A5
A4
A3
A2
QFN PIN #
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
NAME
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
V
REF
IOVDD
PENIRQ
DOUT
BUSY
DIN
CS
DCLK
DESCRIPTION
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
Battery Monitor Input
Auxiliary Input to ADC
Voltage Reference Input/Output
Digital I/O Power Supply
Pen Interrupt
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
Busy Output. This output is high impedance when CS is high.
Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
X–
8
4
TSC2046
www.ti.com
SBAS265C
BURR-BROWN [ BURR-BROWN CORPORATION ]
