Data Sheet
150mA RF ULDO REGULATOR
Pin Configuration
K Package
(SOT-23-5)
AP2202
V
IN
GND
EN
1
2
3
5
V
OUT
V
IN
GND
1
2
3
5
V
OUT
4
BYP
EN
4
ADJ
R Package
(SOT-89-3)
3
2
1
V
IN
GND (TAB)
V
OUT
Figure 2. Pin Configuration of AP2202 (Top View)
Pin Description
Pin Number
SOT-23-5
1
2
3
4
5
1
SOT-89-3
3
2
Pin Name
V
IN
GND
EN
BYP/ADJ
V
OUT
Input voltage
Ground (TAB for SOT-89-3)
Enable input: CMOS or TTL compatible input. Logic high=enable, logic
low=shutdown
Bypass capacitor for low noise operation/Adjust output
Regulated output voltage
Function
Mar. 2007 Rev. 1. 7
2
BCD Semiconductor Manufacturing Limited