Preliminary Datasheet
3-PIN MICROPROCESSOR RESET CIRCUIT
Operating Diagram
V
CC
AZ809A
V
TH
V
CC
(min)
Time
RESET
20
µ
A
Typical
240mS
Typical
240mS
Typical
Reset Active
Timeout Period
Output
Undefined
Time
The AZ809A asserts a reset signal LOW whenever the VCC supply voltage is below the threshold
voltage and remains asserted for 240ms typically after the VCC has risen above the threshold.
Figure 11. Reset Timing Diagram of AZ809A
Application Information
Valid RESET with V
CC
under 1.0 V
The AZ809A RESET output is valid to V
CC
=1.0V.
Below this voltage, the output becomes an open circuit
and doesn't sink current. Therefore, high-impedance
CMOS logic input connected to RESET can drift to
undetermined voltages.
To ensure that the AZ809A RESET is in a known state
when V
CC
is under 1.0V, a 100KΩ pull-down resistor
between the RESET pin and GND is recommended to
discharge stray capacitances and maintain the output
low.
VCC
AZ809A
RESET
GND
R1
100kΩ
Figure 12. RESET Valid to V
CC
=0V
Jan. 2008 Rev. 1. 0
8
BCD Semiconductor Manufacturing Limited
BCDSEMI [ BCD SEMICONDUCTOR MANUFACTURING LIMITED ]
