4�½�MASK LCD型单片机芯片BL2456
INT1 is selectable.
Only INT0 is synchronized with
the system clock.
INT2
KS0–KS3
CLO
BUZ
I
I/O
I/O
I/O
Quasi-interrupt with detection
of rising edge signals.
Quasi-interrupt
input
falling edge detection.
CPU clock output.
2, 4, 8 or 16 kHz frequency output
for buzzer sound with 4.19 MHz
main system clock or 32.768 kHz
subsystem clock.
Crystal, ceramic or RC oscillator
pins for main system clock.
For external clock input, use XIN
and input XIN’s reverse phase to
XOUT.
Crystal oscillator pins for
subsystem clock.
For external clock input, use
XTIN and input XTIN’s reverse
phase to XTOUT.
Main power supply.
Ground.
Reset signal.
Test signal input (must be
connected to VSS).
with
19
29-32
23
24
P1.2
P6.0-P6.3
P2.2
P2.3
Input
Input
Input
Input
A-4
D
D
D
XIN, XOUT
-
12,11
-
-
-
XTIN, XTOUT
-
14,15
-
-
-
VDD
VSS
RESET
TEST
-
-
-
-
9
10
16
13
-
-
-
-
-
-
Input
-
-
-
B
-
注：�½�
I / O
端口被设值为输出模式时上拉电阻自动禁止。
管脚电路图：
管脚电路图：
Type A
http://www.belling.com.cn
Type C
-4-
Total
11 Pages
8/24/2006
Wrote by dipeng
BELLING [ SHANGHAI BELLING CO., LTD. ]
