上海贝岭股½有限公司
上海贝岭股½有限公司
Shanghai Belling Co., Ltd.
BL35P02 DATASHEET
6.7.1 Keyboard Interrupt (KBI)
Keyboard interrupt function is associated with Port A pins and PB0 pin. The keyboard interrupt function is
enabled by setting the keyboard interrupt enable bit KBIE (bit 7 of MCR at $0C) and the individual enable bits
KBE0-KBE7 (bits 0-7 KBIM at $0B) and KBEB0 (bit 0 of DDRB). When the KBEx bit is set, the
corresponding Port A pin will be configure as an input pin, regardless of the DDR setting, and a 25kΩ pull-up
resistor is connected to the pin, as shown in Figure 6.7.1.1. When a high to low transition is sensed on the pin, a
keyboard interrupt will be generated. An interrupt to the CPU will be generated if the I-bi in the CCR is cleared.
The keyboard interrupt flag should be cleared in the interrupt service routine (by writing a “1” to KBIC bit
in the MCR at $0C) after the key is debounced. Deboncing will avoid spurious false triggering.
The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the
contents in $1FF4-$1FF5.
Figure 6.7.1.1
6.7.2 Timer Interrupt
The timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. The interrupt
enable and flag for the timer interrupt are located in the Timer Control Register (TCR).
(1) Timer Interrupt Mask (TIM). When TIM is equal to “1”, Timer interrupt is disabled. When TIM is
equal to “0”, Timer interrupt is enabled.
(2) Timer Interrupt Flag (TIF). When TIF is equal to “1”, A timer interrupt (timer overflow) has occurred.
When TIF is equal to “0”, A timer interrupt (timer overflow) has not occurred.
The I-bit in the CCR must be cleared in order for the timer interrupt to be processed. The interrupt will
vector to the interrupt service routine at the address specified by the contents in $1FF6-$1FF7.
6.7.3 Interrupts Process
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit)
to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete. The current instruction is the on already fetched
and being operated on. When the current instruction is complete, the processor checks all pending hardware
interrupts. If interrupts are not masked (CCR I-bit clear) the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed. The relative priority of all the possible sources is shown
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