OVERVIEW
PLL
25 MHz
PLL
DDR/SDRAM
Interface
EJTAG
MIPS32
Core
MMU
USB2 Host Ports
2
PCI 32/33
Up to four
PCI Master
48 MHz
USB2 Device Port
USB2.0
Device
2-port
USB2.0
EHCI
I-Cache
(32 KB)
D-Cache
(32 KB)
DDR/SDRAM
Interface
Bus I/F
PCI Interface
Internal Bus
EBI/GPIO
Dual RS232
UART
10/100/1000
MAC
Flash, GPIOs
Enclosure Mgmt
Thermal Mgmt
Two UART
interfaces
RGMII/GMII/MII
Interface
BCM4705 Block Diagram
The Broadcom BCM4705 processor is the highest performance chip in
the 802.11n/MIMO Intensi-fi™ processor family.
It integrates a powerful 300 MHz/500 DMIPS (*estimated) MIPS32 core
with 4-way set associative 32 KB instruction cache, a 32 KB 2-way set
associative data cache, and a 4 KB prefetch cache. An enhanced 10/100/
1000 Gigabit Ethernet MAC controller with TCP Segmentation and
checksum Offload (TSO) hardware acceleration engine substantially
enhances system throughput.
The BCM4705 integrates two USB2.0 EHCI Host ports and one USB2.0
Device port. The USB2.0 device port allows connectivity to PC or
consumer electronics (CE) devices equipped with USB host ports.
The BCM4705 supports a PCI 2.3 host interface and a USB host/device
interface for adding application-specific peripherals including
BCM4321 2x2 MIMO, BCM4318 single-chip 802.11g, BCM4309
802.11 a/b/g, BCM4320 USB2.0 WLAN, BCM5397 Gigabit Ethernet
switch, and future generations of Broadcom wired, wireless, audio/video
codec, and multimedia processing devices.
Broadcom
®
, the pulse logo,
Connecting everything
®
, and the Connecting everything logo are among
the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries
and/or the EU. Any other trademarks or trade names mentioned are the property of their respective
owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2006 by BROADCOM CORPORATION. All rights reserved.
4705-PB00-R
12/05/06
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BOARDCOM [ Broadcom Corporation. ]
