BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Dual CE Pins)
BS616LV8016
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.)
CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.)
CMOS standby current
• High speed access time :
-55
-70
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV8016 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of
1.5uA
at 3V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV8016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8016 is available in 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.4V ~ 5.5V
2.4V ~ 5.5V
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=3V
Vcc=5V
Vcc=3V
70ns
Vcc=5V
70ns
BS616LV8016FC
BS616LV8016FI
55 / 70
55 / 70
5uA
10uA
55uA
110uA
24mA
25mA
60mA
61mA
BGA-48-0912
BGA-48-0912
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
2
OE
UB
D10
D11
3
A0
A3
A5
A17
VSS
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
WE
A11
6
CE2
D0
D2
VCC
VSS
D6
D7
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16
Data
Input
Buffer
16
Column I/O
VCC
D14
D15
A 18
D12
D13
NC
.
A8
.
.
.
.
D15
CE2
CE1
WE
OE
UB
LB
.
.
.
.
Write Driver
Sense Amp
256
Column Decoder
16
Data
Output
16
Buffer
16
Control
Address Input Buffer
NC
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV8016
1
Revision 2.1
Jan.
2004
BSI [ BRILLIANCE SEMICONDUCTOR ]
