Very Low Power CMOS SRAM
128K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV2016
FEATURES
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Operation current : 30mA (Max.) at 55ns
V
CC
= 3.0V
2mA (Max.) at 1MHz
O
Standby current : 0.7/2uA (Max.) at 70/85 C
Operation current : 62mA (Max.) at 55ns
V
CC
= 5.0V
8mA (Max.) at 1MHz
O
Standby current : 6/20uA (Max.) at 70/85 C
High speed access time :
-55
55ns(Max.) at V
CC
=3.0~5.5V
-70
70ns(Max.) at V
CC
=2.7~5.5V
Automatic power down when chip is deselected
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
DESCRIPTION
The BS616LV2016 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 2/20uA at Vcc=3V/5V at 85 C and maximum access time
of 55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV2016 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2016 is available in DICE form, JEDEC standard
44-pin TSOP II package and 48-ball BGA package.
O
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS616LV2016DC
BS616LV2016EC
BS616LV2016AI
BS616LV2016EI
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
Commercial
O
O
+0 C to +70 C
DICE
6.0uA
0.7uA
7mA
39mA
60mA
1.5mA
14mA
29mA
TSOP II-44
BGA-48-0608
20uA
2.0uA
8mA
40mA
62mA
2mA
15mA
30mA
TSOP II-44
Industrial
O
-40 C to +85 C
O
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
A2
CE
D1
D3
D4
D5
WE
A11
6
NC
D0
D2
VCC
VSS
D6
D7
NC
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
BS616LV2016EC
BS616LV2016EI
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
.
.
.
.
.
.
DQ15
16
.
.
.
.
.
.
16
Data
Output
Buffer
16
128
Column Decoder
7
Control
Address Input Buffer
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
2
OE
UB
D10
D11
D12
D13
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
CE
WE
OE
UB
LB
V
CC
V
SS
A12 A13 A14 A15 A16 A0
A1
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS66LV2016
1
Revision
1.5
Oct.
2008
BSI [ BRILLIANCE SEMICONDUCTOR ]
