BSI
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV2016
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
55
--
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
--
--
30
30
25
--
70
--
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
NOTE :
1. t
BA
is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t
BA
is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV2016
4
Revision 1.1
Jan.
2004
BSI [ BRILLIANCE SEMICONDUCTOR ]
