BSI
BS62LV1027
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
READ CYCLE
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
UNIT
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQV
tE1LQV
tE2HOV
tGLQV
tE1LQX
tE2HOX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
Read Cycle Time
tRC
tAA
55
--
--
--
--
--
--
--
--
--
--
--
--
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
55
55
55
30
--
70
70
70
40
--
tACS1
tACS2
tOE
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
Chip Select Access Time
(CE1)
(CE2)
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
(CE1)
(CE2)
10
10
10
--
10
10
10
--
--
--
--
--
(CE1)
(CE2)
35
35
30
40
40
35
--
--
--
--
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
Revision 2.1
R0201-BS62LV1027
4
Jan.
2004
BSI [ BRILLIANCE SEMICONDUCTOR ]
