BS62LV1600
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR
≧1.5V
V
CC
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 55ns
(V
CC
=3.0~5.5V)
MIN. TYP. MAX.
55
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
25
--
--
--
30
30
25
--
CYCLE TIME : 70ns
(V
CC
= 2.7~5.5V)
MIN. TYP. MAX.
70
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
30
--
--
--
35
35
30
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
O
O
t
AVAX
t
AVQX
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
R0201-BS62LV1600
4
Revision 2.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
