Very Low Power CMOS SRAM
256K X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV2006
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V Operation current : 23mA (Max.)
2mA (Max.)
Standby current : 0.1uA (Typ.)
V
CC
= 5.0V Operation current : 55mA (Max.)
10mA (Max.)
Standby current : 0.6uA (Typ.)
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
:
3.0~5.5V
-70
70ns (Max.) at V
CC
:
2.7~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE2, CE1 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
at 55ns
at 1MHz
at 25
O
C
at 55ns
at 1MHz
at 25
O
C
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DESCRIPTION
The BS62LV2006 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.1uA at 3.0V/25
O
C and maximum access time of 55ns at
3.0V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV2006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, 8mmx20mm TSOP and
36-ball BGA package.
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POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV2006DC
BS62LV2006HC
BS62LV2006SC
BS62LV2006STC
BS62LV2006TC
BS62LV2006HI
BS62LV2006SI
BS62LV2006STI
BS62LV2006TI
Industrial
-40
O
C to +85
O
C
20uA
2.0uA
10mA
30mA
55mA
2mA
10mA
23mA
Commercial
+0
O
C to +70
O
C
6.0uA
0.7uA
9mA
29mA
53mA
1.5mA
9mA
22mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5V
10MHz
f
Max.
1MHz
DICE
BGA-36-0608
SOP-32
STSOP-32
TSOP-32
BGA-36-0608
SOP-32
STSOP-32
TSOP-32
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PIN CONFIGURATIONS
n
BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A7
A12
A14
A16
A17
A15
A11
A8
A9
A13
•
BS62LV2006TC
BS62LV2006TI
BS62LV2006STC
BS62LV2006STI
1
2
A1
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
DQ1
DQ2
DQ3
5
A6
6
A8
8
Data
Input
Buffer
8
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
8
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
•
3
CE2
4
A3
BS62LV2006SC
BS62LV2006SI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A
A0
B
DQ4
A2
WE
A4
A7
DQ0
DQ4
DQ5
DQ6
DQ7
8
Data
Output
Buffer
C
DQ5
NC
A5
DQ1
D
VSS
VCC
E
VCC
VSS
CE2
CE1
WE
OE
V
CC
GND
Control
Address Input Buffer
F
DQ6
NC
A17
DQ2
A6 A5 A10 A4 A3 A2 A1 A0
G
DQ7
OE
CE1
A16
A15
DQ3
H
A9
A10
A11
A12
A13
A14
36-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV2006
1
Revision 1.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
