Very Low Power CMOS SRAM
32K X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV256
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V Operation current : 25mA (Max.) at 70ns
1mA (Max.) at 1MHz
Standby current : 0.01uA(Typ.) at 25
O
C
V
CC
= 5.0V Operation current : 40mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.4uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns(Max.) at V
CC
:
4.5~5.5V
-70
70ns(Max.) at V
CC
:
3.0~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
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DESCRIPTION
The BS62LV256 is a high performance, very low power CMOS Static
Random Access Memory organized as 32,768 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.01uA and maximum access time of 70ns in 3.0V
operation.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV256 is available in DICE form, JEDEC standard 28 pin
330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP
(normal type).
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POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV256DC
BS62LV256PC
BS62LV256SC
BS62LV256TC
BS62LV256PI
BS62LV256SI
BS62LV256TI
Industrial
-40
O
C to +85
O
C
5.0uA
0.7uA
2mA
20mA
40mA
1mA
15mA
25mA
Commercial
+0
O
C to +70
O
C
4.0uA
0.4uA
1.5mA
18mA
35mA
0.8mA
12mA
20mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
DICE
PDIP-28
SOP-28
TSOP-28
PDIP-28
SOP-28
TSOP-28
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PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
n
BLOCK DIAGRAM
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
•
BS62LV256PC
BS62LV256PI
BS62LV256SC
BS62LV256SI
A5
A6
A7
A12
A14
A13
A8
A9
A11
Address
Input
Buffer
9
Row
Decoder
512
Memory Array
512X512
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
64
Column Decoder
6
CE
WE
OE
V
CC
GND
A4 A3 A2 A1 A0 A10
Control
Address Input Buffer
8
Column I/O
Write Driver
Sense Amp
8
Data
Output
Buffer
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV256TC
BS62LV256TI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV256
1
Revision 2.6
Sep.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
