Very Low Power CMOS SRAM
1M X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV8001
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V
Operation current : 31mA (Max.)
2mA (Max.)
Standby current : 0.8uA (Typ.)
V
CC
= 5.0V
Operation current : 76mA (Max.)
10mA (Max.)
Standby current : 3.5uA (Typ.)
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
: 3.0~5.5V
-70
70ns (Max.) at V
CC
: 2.7~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS62LV8001 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
at 55ns
at 1MHz
O
at 25 C
at 55ns
at 1MHz
O
at 25 C
and operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.8uA at 3.0V/25 C and maximum access time of 55ns at
3.0V/85 C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
TSOP II and 48-ball BGA package.
O
O
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV8001DC
BS62LV8001EC
BS62LV8001FC
BS62LV8001EI
BS62LV8001FI
Industrial
O
-40 C to +85 C
O
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
DICE
Commercial
O
O
+0 C to +70 C
25uA
4.0uA
9mA
39mA
75mA
1.5mA
19mA
30mA
TSOP II-44
BGA-48-0912
50uA
8.0uA
10mA
40mA
76mA
2mA
20mA
31mA
TSOP II-44
BGA-48-0912
n
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
VSS
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
A
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
OE
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
A2
6
CE2
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
VSS
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
n
BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
BS62LV8001EC
BS62LV8001EI
2048 x 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
512
Column Decoder
18
Control
Address Input Buffer
8
Column I/O
Write Driver
Sense Amp
8
3
A0
4
A1
Data
Output
Buffer
B
C
NC
DQ0
NC
NC
A3
A5
A4
A6
CE1
NC
NC
DQ4
D
VSS
DQ1
A17
A7
DQ5
VCC
CE1
CE2
WE
OE
V
CC
V
SS
A11 A9 A8 A3 A2 A1 A0 A10 A19
E
VCC
DQ2
NC
A16
DQ6
VSS
F
DQ3
NC
A14
A15
NC
DQ7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV8001
1
Revision
2.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
