Data Sheet
Electrical Characteristics - CDK1307C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
71.6
72.6
71.8
71.5
70.4
71.7
71.7
71.1
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
70.5
75
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
81
84
dBc
79
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
77
dBc
-85
-75
11.4
-95
-95
-95
-95
-81
-84
-79
-79
11.6
11.6
11.5
11.3
dBc
dBc
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
bits
bits
ENOB
bits
FIN = 40MHz
bits
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
20.4
2.3
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
5.1
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
3.5
mA
Analog Power Dissipation
Digital Power Dissipation
36.7
12.9
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
49.6
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode
9.3
μW
Power Dissipation, Sleep mode
20.4
mW
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
65
MSPS
MSPS
40
©2009 CADEKA Microcircuits LLC
www.cadeka.com
8
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