ADVANCE
Data Sheet
Electrical Characteristics - CDK1307A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
F
IN
= 2MHz
Min
Typ
72.7
72.6
72.3
72.0
72.4
72.0
71.3
71.4
84.9
88.7
80.1
85.5
-97.6
-100
-101
-95.7
-94.6
-88.7
-80.1
-96.8
11.7
11.7
11.6
11.6
7.8
Max
Units
CDK1307
Ultra Low Power, 20/40/65/80MSPS, 12/13-bit ADCs
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
mA
mA
mA
mA
mW
mW
mW
μW
mW
MSPS
15
MSPS
SNR
Signal to Noise Ratio
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
F
IN
= 2MHz
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
F
IN
= 2MHz
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
F
IN
= 2MHz
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
F
IN
= 2MHz
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
F
IN
= 2MHz
F
IN
= 8MHz
F
IN
≃
FS/2
F
IN
= 20MHz
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
Power Supply
AI
DD
DI
DD
Analog Supply Current
Digital Supply Current
Digital core supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT enabled
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode
20
1.0
1.7
1.3
14.0
5.1
19.1
9.9
9.2
OI
DD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Total Power Dissipation
Power Down Dissipation
Sleep Mode
Rev 0.1
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2008 CADEKA Microcircuits LLC
www.cadeka.com
6
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
