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CDK8307EITQ80 参数 Datasheet PDF下载

CDK8307EITQ80图片预览
型号: CDK8307EITQ80
PDF下载: 下载PDF文件 查看货源
内容描述: 12月13日位,四十零分之二十零/ 50/ 65 / 80MSPS ,八通道,超低功耗ADC LVDS [12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS]
分类和应用:
文件页数/大小: 31 页 / 1408 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel,
Ultra Low Power ADC with LVDS
FEATURES
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CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
General Description
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
20/40/50/65/80MSPS max sampling rate
Low Power Dissipation
– 23mW/channel at 20MSPS
– 35mW/channel at 40MSPS
– 41mW/channel at 50MSPS
– 51mW/channel at 65MSPS
– 59mW/channel at 80MSPS
72.2dB SNR at 8MHz F
IN
0.5μs startup time from Sleep
15μs startup time from Power Down
Internal reference circuitry requires no
external components
Internal offset correction
Reduced power dissipation modes available
– 34mW/channel at 50MSPS
– 71.5dB SNR at 8MHz F
IN
Coarse and fine gain control
1.8V supply voltage
Serial LVDS output
– 12- and 14-bit output available
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Block Diagram
RESETN
SCLK
SDATA
AVDD
AVSS
DVDD
DVSS
LVDS
FCLKP
FCLKN
LCLKP
LCLKN
D1N
D1P
D2N
D2P
LVDS
LVDS
CLKP
CLKN
CSN
PD
PLL
Digital
Gain
Digital
Gain
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Package alternatives
– TQFP-80
– QFN-64
APPLICATIONS
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Medical Imaging
Wireless Infrastructure
Test and Measurement
Instrumentation
IP2
IN2
IP1
IN1
Serial Control
Interface
ADC
Clock
Input
ADC
IP8
IN8
ADC
Digital
Gain
LVDS
D8N
D8P
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com