Data Sheet
Maximum Power Dissipation (W)
In order to determine P
D
, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
P
D
= P
supply
- P
load
Supply power is calculated by the standard power
equation.
P
supply
= V
supply
× I
RMS supply
V
supply
= V
S+
- V
S-
Power delivered to a purely resistive load is:
P
load
= ((V
LOAD
)
RMS
2
)/Rload
eff
The effective load resistor (Rload
eff
) will need to include
the effect of the feedback network. For instance,
Rload
eff
in figure 3 would be calculated as:
R
L
|| (R
f
+ R
g
)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
D
can be found from
P
D
= P
Quiescent
+ P
Dynamic
- P
Load
Quiescent power can be derived from the specified I
S
values along with known supply voltage, V
Supply
. Load
power can be calculated as above with the desired signal
amplitudes using:
(V
LOAD
)
RMS
= V
PEAK
/ √2
( I
LOAD
)
RMS
= ( V
LOAD
)
RMS
/ Rload
eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
DYNAMIC
= (V
S+
- V
LOAD
)
RMS
× ( I
LOAD
)
RMS
Assuming the load is referenced in the middle of the
power rails or V
supply
/2.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the packages
available.
2
SOIC-8
1.5
MSOP-8
C
omlinear
CLC1011, CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
1
0.5
SOT23-6
SOT23-5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 4. Maximum Power Derating
Input Common Mode Voltage
The common mode input range extends to 250mV below
ground and to 250mV above Vs, in single supply operation.
Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition.
If the absolute maximum input voltage (700mV beyond
either rail) is exceeded, externally limit the input current to
±5mA as shown in Figure 5.
10k
Input
Output
Figure 5. Circuit for Input Current Protection
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency
response, and possible unstable behavior. Use a series
resistance, R
S
, between the amplifier and the load to
help improve stability and settling performance. Refer to
Figure 6.
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
