Data Sheet
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa
has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 1µF and 0.1µF ceramic capacitors for power sup-
ply decoupling
• Place the 6.8µF capacitor <0.75 inches of the power pin
• Place the 0.1µF capacitor <0.1 inches of the power pin
• Remove the ground plane near the input and output pins
to reduce parasitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts for more informa-
tion.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board
CEB021
Products
CLC3800, CLC3801, CLC3802 in
SOIC packages
Figure 10. CEB021 Top View
C
omlinear
CLC3800, CLC3801, CLC3802
Triple,
Standard Definition Video Amplifiers
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 9-11. Application Note AN-6 provides a detailed de-
scription of the evaluation board.
Figure 11. CEB006 Bottom View
SHORT FOR CLC3800/CLC3801/CLC3802
Rev 1A
Figure 9. CEB021 Schematic
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
8
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
