Data Sheet
Maximum Power Dissipation (W)
In order to determine P
D
, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
P
D
= P
supply
- P
load
Supply power is calculated by the standard power equa-
tion.
P
supply
= V
supply
× I
RMS supply
V
supply
= V
S+
- V
S-
Power delivered to a purely resistive load is:
P
load
= ((V
LOAD
)
RMS
2
)/Rload
eff
The effective load resistor (Rload
eff
) will need to include
the effect of the feedback network. For instance,
Rload
eff
in figure 3 would be calculated as:
R
L
|| (R
f
+ R
g
)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
D
can be found from
P
D
= P
Quiescent
+ P
Dynamic
- P
Load
Quiescent power can be derived from the specified I
S
val-
ues along with known supply voltage, V
Supply
. Load power
can be calculated as above with the desired signal ampli-
tudes using:
(V
LOAD
)
RMS
= V
PEAK
/ √2
( I
LOAD
)
RMS
= ( V
LOAD
)
RMS
/ Rload
eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
DYNAMIC
= (V
S+
- V
LOAD
)
RMS
× ( I
LOAD
)
RMS
Assuming the load is referenced in the middle of the power
rails or V
supply
/2.
Figure 8 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8 and 14 lead
SOIC packages.
2.5
2
SOIC-14
1.5
Comlinear
™
CLC2601, CLC3601, CLC4601
Dual, Triple, and Quad 550MHz Amplifiers
1
SOIC-8
0.5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 8. Maximum Power Derating
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
In addition, increased airflow across the package can also
help to reduce the effective Ө
JA
of the package.
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA
has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.01µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Rev 1C
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
