DATA SHEET
KH207
Inverting gain applications:
s
s
s
Connect R
3
directly to ground.
Make the resistors R
4
, R
6
, and R
7
equal to Z
o
.
Make R
5
II R
g
= Z
o
.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
6
to match the output transmission line over a
greater frequency range. C
6
compensates for the increase
of the amplifier’s output impedance with frequency.
Dynamic Range (Intermods)
For RF applications, the KH207 specifies a third
order intercept of 26dBm at 60MHz and P
o
= 10dBm. A
2-Tone, 3rd Order IMD Intercept
plot is found in the
Typical Performance Characteristics
section. The out-
put power level is taken at the load. Third-order harmon-
ic distortion is calculated with the formula:
HD 3
rd
= 2
•
(IP3
o
– P
o
)
where:
s
s
s
s
Printed Circuit Layout
As with any high frequency device, a good PCB layout
will enhance the performance of the KH207. Good
ground plane construction and power supply bypassing
close to the package are critical to achieving full perfor-
mance. In the non-inverting configuration, the amplifier is
sensitive to stray capacitance to ground at the inverting
input. Hence, the inverting node connections should be
small with minimal stray capacitance to the ground plane
or other nodes. Shunt capacitance across the feedback
resistor should not be used to compensate for this effect.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
s
s
s
IP3
o
= third-order output intercept, dBm at
the load.
P
o
= output power level, dBm at the load.
HD 3
rd
= third-order distortion from the
fundamental, -dBc.
dBm is the power in mW, at the load,
expressed in dB.
s
s
s
Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3
rd
order
distortion are:
s
s
s
s
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75
inches of the power pins.
Place the 0.1µF capacitors less than 0.1
inches from the power pins.
Remove the ground plane under and
around the part, especially near the input
and output pins to reduce parasitic
capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins
for prototyping, never use high profile DIP
sockets.
short and equal return paths from the load
to the supplies.
de-coupling capacitors of the correct value.
higher load resistance.
a lower ratio of the output swing to the
power supply voltage.
An evaluation PC board (part number 730009) for the
KH207 is available to aid in device testing.
6
REV. 1A January 2004
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
